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en23f0qi 15a voltage mode synchronous buck pwm dc-dc converter with integrated inductor www.enpirion.com description the en23f0qi is a power system on a chip (powersoc) dc-dc converter. it integrates mosfet switches, small-signal control circuits, compensation and an integrated inductor in an advanced 12x13x3mm qfn module. it offers high efficiency, excellent line and load regulation. the en23f0qi operates over a wide input voltage range and is specifically designed to meet the precise voltage and fast transient requirements of high-performance products. the en23f0qi features frequency synchronization to an external clock, power ok output voltage monitor, programmable soft-start along with thermal and over current protection. the device?s advanced circuit design, ultra high switching frequency and proprietary integrated inductor technology delivers high-quality, ultra compact, non- isolated dc-dc conversion. the enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. in addition, overall system level reliability is improved gi ven the small number of components required with the enpirion solution. all enpirion products are rohs compliant and lead- free manufacturing environment compatible. features ? integrated inductor, mosfets, controller ? total solution size estimate 308mm 2 ? wide input voltage range: 4.5v ? 14v ? 2% v out accuracy (over line/load/temperature) ? master/slave configuration for parallel operation o up to 4 devices with 48a capability ? frequency synchronization (external clock) ? output enable pin and power ok signal ? programmable soft-start time ? under voltage lockout protection (uvlo) ? programmable over current protection ? thermal shutdown and short circuit protection ? rohs compliant, msl level 3, 260 o c reflow applications ? space constrained applications ? distributed power architectures ? output voltage ripple sensitive applications ? beat frequency sensitive applications ? servers, embedded computing systems, lan/san adapter cards, raid storage systems, industrial automation, test and measurement, and telecommunications figure 1. simplified applications circuit (footprint optimized) figure 2. highest efficiency in smallest solution size 0 10 20 30 40 50 60 70 80 90 100 0123456789101112131415 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 1.8v vout = 1.2v conditions v in = 12.0v avin = 3.3v dual supply
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 2 ordering information part number package markings temp rating (c) package description en23f0qi en23f0qi -40 to +85 92-pin (12mm x 13mm x 3mm) qfn t&r en23f0qi-e en23f0qi qfn evaluation board packing and marking information : http://www.enpirion.com/resource-center-packing-and-marking-information.htm pin assignments (top view) figure 3: pin out diagram (top view) note a : nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to fo llow this guideline may result in part malfunction or damage. note b : shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected to the pcb. refer to figure 14 for details. note c : white ?dot? on top left is pin 1 indicator on top of the device package.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 3 pin description i/o legend : p=power g=ground nc=no connect i=input o=output i/o=input/output pin name i/o function 1-24, 36, 81 nc nc no connect ? these pins may be internally connected. do not connect them to each other or to any other electrical signal. failur e to follow this guideline may result in device damage. 25-35 vout o regulated converter output. connect these pins to the load and place output capacitor between these pins and pgnd pins 40-42. 37-39, 83-92 nc(sw) nc no connect ? these pins are internally connected to the common switching node of the internal mosfets. they are not to be electrica lly connected to any external signal, ground, or voltage. failure to follow this guideli ne may result in damage to the device. 40-46 pgnd g input/output power ground. connect these pins to the ground electrode of the input and output filter capacitors. see vout and pvin pin descriptions for more details. 47-63 pvin p input power supply. connect to input power su pply. decouple with input capacitor to pgnd pins 43-46. 64 avino o internal 3.3v linear regulator output. connect this pin to avin (pin 73) for applications where operation from a single input voltage ( pvin) is required. if avino is being used, place a 1f, x5r/x7r, capacitor between avi no and agnd as close as possible to avino. 65 pg i/o place a 0.1f, x7r, capacitor between this pin and btmp. 66 btmp i/o see pin 65 description. 67 vddb o internal regulated voltage used for the internal c ontrol circuitry. place a 1f, x7r, capacitor between this pin and bgnd. 68 bgnd g see pin 67 description. 69 s_in i digital input. this pin accepts either an input clock to phase lock the internal switching frequency or a s_out signal from another en 23f0qi. leave this pin floating if not used. 70 s_out o digital output. pwm signal is output on this pin. leave this pin floating if not used. 71 pok o power ok is an open drain transistor (pulled up to avin or similar voltage) used for power system state indication. pok is logic high when vout is -10% of vout nominal. leave this pin floating if not used. 72 enable i input enable. applying a logic high to this pi n enables the output and initiates a soft-start. applying a logic low disables the output. do not leave this pin floating. 73 avin p 3.3v input power supply for the controller. place a 0.1f, x7r, capacitor between avin and agnd. 74 agnd g analog ground. this is the ground return for the controller. needs to be connected to a quiet ground. 75 m/s i a logic level low configures the device as ma ster and a logic level high configures the device as a slave. connect to ground in standalone mode. 76 vfb i/o external feedback input. the feedback loop is closed through this pin. a voltage divider at vout is used to set the output voltage. the mid- point of the divider is connected to vfb. a phase lead capacitor from this pin to vo ut is also required to stabilize the loop. 77 eain o optional error amplifier input. allows for cust omization of the control loop for performance optimization. leave this pin floating if unused. 78 ss i/o soft-start node. the soft-start capacitor is connected between this pin and agnd. the value of this capacitor determines the star tup time. see soft-start operation in the functional description section for details. 79 rclx i/o programmable over-current protec tion. placement of a resistor on this pin will adjust the over-current protection threshold. see table 2 for the recommended rclx value to set ocp at the nominal value specified in the electr ical characteristics table. no current limit protection when this pin is left floating. 80 fadj i/o adding a resistor (r fs ) to this pin will adjust the swit ching frequency of the en23f0qi. see table 1 for suggested resistor values on r fs for various pvin/vout combinations to maximize efficiency. do not leave this pin floating. 82 cgnd g connect to gnd plane at all times. 93 pgnd g not a perimeter pin. device thermal pad to be connected to the system gnd plane for heat- sinking purposes.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 4 absolute maximum ratings caution : absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute ma ximum ratings may impair device life. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min max units voltages on : pvin, vout -0.5 15 v pin voltages ? avino, avin, enable, po k, s_in, s_out, m/s 2.5 6.0 v pin voltages ? vfb, ss, eain, rclx, fadj -0.5 2.75 v pvin slew rate 0.3 3 v/ms storage temperature range t stg -65 150 c maximum operating junction temperature t j-abs max 150 c reflow temp, 10 sec, msl3 jedec j-std-020a 260 c esd rating (based on human body model) 2000 v esd rating (based on cdm) 500 v recommended operating conditions parameter symbol min max units input voltage range pvin 4.5 14.0 v avin: controller supply voltage avin 2.5 5.5 v output voltage range (note 1) v out 0.75 3.3 v output current i out 15 a operating ambient temperature t a -40 +85 c operating junction temperature t j -40 +125 c thermal characteristics parameter symbol typ units thermal shutdown t sd 160 c thermal shutdown hysteresis t sdh 35 c thermal resistance: junction to ambient (0 lfm) (note 2) ja 13 c/w thermal resistance: junction to case (0 lfm) jc 1 c/w note 1 : rclx resistor value may need to be raised for v out > v in ? 2.5v to increase current limit threshold. contact techsupport@enpirion.com for details. note 2 : based on 2oz. external copper layers and proper thermal design in line wi th eij/jedec jesd51-7 standard for high thermal conductivity boards.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 5 electrical characteristics note: v in =12v, minimum and maximum values are over operating ambient temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ max units operating input voltage pvin 4.5 14.0 v controller input voltage avin 2.5 5.5 v pvin under voltage lock-out uvlo pvin voltage above which uvlo is not asserted 2 v avin under voltage lock-out rising avin uvlor voltage above which uvlo is not asserted 2.3 v avin under voltage lock-out falling avin ovlof voltage below which uvlo is asserted 2.1 v avin pin input current i avin 14 ma internal linear regulator output voltage avino 3.3 v shut-down supply current ipvin s pvin=12v, avin=3.3, enable=0v 300 a iavin s pvin=12v, avin=3.3, enable=0v 50 a feedback pin voltage v fb feedback node voltage at: v in = 12v, iload = 0, t a = 25c 0.594 0.60 0.606 v feedback pin voltage v fb feedback node voltage at: 4.5v v in 14v 0a i load 15a, t a = -40 to 85c 0.588 0.60 0.612 v feedback pin input leakage current i fb vfb pin input leakage current (note 3) -5 5 na v out rise time t rise c ss = 47nf (note 3, note 4 and note 5) 1.96 2.8 3.64 ms soft start capacitor range c ss_range 47 nf continuous output current i out_cont 0 15 a over current trip level i ocp reference table 3 22.5 a enable logic high v enable_high 4.5v v in 14v; 1.8 av in v enable logic low v enable_low 4.5v v in 14v; 0 0.6 v enable lockout time t enlockout 8 ms enable pin input current i enable 180k pull down (note 3) 4 a switching frequency f sw rfadj =3k ? 1.0 mhz external sync clock frequency lock range f pll_lock range of sync clock frequency 0.8 1.6 mhz s_in threshold ? low v s_in_lo s_in clock logic low level 0.8 v s_in threshold ? high v s_in_hi s_in clock logic high level 1.8 2.5 v s_out threshold ? low v s_out_lo s_out clock logic low level 0.8 v s_out threshold ? high v s_out_hi s_out clock logic high level 1.8 2.5 v pok lower threshold pok lt percentage of nominal output voltage for pok to be low 90 %
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 6 parameter symbol test conditions min typ max units pok output low voltage v pokl with 4ma current sink into pok 0.4 v pok output hi voltage v pokh pvin range: 4.5v v in 15v avin v pok pin v oh leakage current i pokl pok high (note 3) 1 a m/s pin logic low v t-low tie pin to gnd 0.8v v m/s pin logic high v t-high pull up to avin through an external resistor rext 1.8v v m/s pin input current i m/s vin = 5.0v, rext = 24.9k 100 a note 3 : parameter not production tested but is guaranteed by design. note 4 : rise time calculation begins when avin > v uvlo and enable = high. note 5 : v out rise time accuracy does not include soft-start capacitor tolerance.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 7 typical performance curves 0 10 20 30 40 50 60 70 80 90 100 0123456789101112131415 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 1.8v vout = 1.2v conditions v in = 12.0v avin = 3.3v dual supply 0 10 20 30 40 50 60 70 80 90 100 0123456789101112131415 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 1.8v vout = 1.2v conditions v in = 10.0v avin = 3.3v dual supply 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating vout = 1.2v vout = 1.8v vout = 3.3v conditions v in = 12v t jmax = 125 c ja = 13 c/w 13x12x3mm qfn no air flow 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating vout = 1.2v vout = 1.8v series1 conditions v in = 10v t jmax = 125 c ja = 13 c/w 13x12x3mm qfn no air flow 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating with air flow (200fpm) vout = 1.2v vout = 1.8v vout = 3.3v conditions v in = 12v t jmax = 125 c ja = 10.5 c/w 13x12x3mm qfn air flow (200fpm) 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating with air flow (400fpm) vout = 1.2v vout = 1.8v vout = 3.3v conditions v in = 12v t jmax = 125 c ja = 9 c/w 13x12x3mm qfn air flow (400fpm)
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 8 typical performance curves 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating with heat sink vout = 1.2v vout = 1.8v vout = 3.3v conditions v in = 12v t jmax = 125 c ja = 12 c/w 13x12x3mm qfn no air flow heat ? sink ?\ wakefield thermal ? solutions ? p/n ? 651 \ b ? 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating with heat sink and air flow (200fpm) vout = 1.2v vout = 1.8v vout = 3.3v conditions v in = 12v t jmax = 125 c ja = 9.5 c/w 13x12x3mm qfn air flow (200fpm) heat sink - wakef ield thermal solutions p/n 651-b 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 25 30 35 40 45 50 55 60 65 70 75 80 85 maximum output current (a) ambient temperature ( c) output current de-rating with heat sink and air flow (400fpm) vout = 1.2v vout = 1.8v vout = 3.3v conditions v in = 12v t jmax = 125 c ja = 8 c/w 13x12x3mm qfn air flow (400fpm) heat sink - wakef ield thermal solutions p/n 651-b 0.995 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 0123456789101112131415 output voltage (v) output current (a) output voltage vs. output current vin = 8v vin = 10v vin = 12v conditions v in = 5.0v conditions v out_nom = 1.0v 1.195 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 1.205 0123456789101112131415 output voltage (v) output current (a) output voltage vs. output current vin = 8v vin = 10v vin = 12v conditions v in = 5.0v conditions v out_nom = 1.2v 1.795 1.796 1.797 1.798 1.799 1.800 1.801 1.802 1.803 1.804 1.805 0123456789101112131415 output voltage (v) output current (a) output voltage vs. output current vin = 8v vin = 10v vin = 12v conditions v out_nom = 1.8v note: air flow or heat sink may be required for higher currents. see derating curves.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 9 typical performance curves 2.495 2.496 2.497 2.498 2.499 2.500 2.501 2.502 2.503 2.504 2.505 0123456789101112131415 output voltage (v) output current (a) output voltage vs. output current vin = 8v vin = 10v vin = 12v conditions v out_nom = 2.5v note: air flow or heat sink may be required for higher currents. see derating curves. 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 4a load = 8a load = 12a conditions v in = 8v v out_nom = 1.2v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 4a load = 8a load = 12a conditions v in = 10v v out_nom = 1.2v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 4a load = 8a load = 12a conditions v in = 12v v out_nom = 1.2v 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 -40 -15 10 35 60 85 output voltage (v) ambient temperature ( c) output voltage vs. temperature load = 0a load = 4a load = 8a load = 12a conditions v in = 14v v out_nom = 1.2v 0 2.5 5 7.5 10 12.5 15 17.5 20 0 5 10 15 20 25 30 individual output current (a) total output current (a) parallel current share breakdown master slave ideal conditions en23f0qi v in = 12v v out = 1.2v
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 10 typical performance characteristics enable enable startup/shutdown waveform (0a) conditions vin = 12v, vout = 3.3v, load = 0a, css = 47nf cin = 3x22f(1206), cout = 3x47f(0805)+3x22f(0805) vout pok load enable enable startup/shutdown waveform (5a) conditions vin = 12v, vout = 3.3v, load = 5a, css = 47nf cin = 3x22f(1206), cout = 3x47f(0805)+3x22f(0805) vout pok load enable enable startup/shutdown waveform (10a) conditions vin = 12v, vout = 3.3v, load = 10a, css = 47nf cin = 3x22f(1206), cout = 3x47f(0805)+3x22f(0805) vout pok load enable enable startup/shutdown waveform (15a) conditions vin = 12v, vout = 3.3v, load = 15a, css = 47nf cin = 3x22f(1206), cout = 3x47f(0805)+3x22f(0805) vout pok load pvin power up waveform (0a) conditions vin = 12v, vout = 3.3v, load = 0a, css = 47nf, cin = 3x22f(1206), cout = 3x47f(0805) + 3x22f(0805) vout pok load pvin power up waveform (5a) conditions vin = 12v, vout = 3.3v, load = 5a, css = 47nf, cin = 3x22f(1206), cout = 3x47f(0805) + 3x22f(0805) vout pok load
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 11 typical performance characteristics pvin power up waveform (15a) conditions vin = 12v, vout = 3.3v, load = 15a, css = 47nf, cin = 3x22f(1206), cout = 3x47f(0805) + 3x22f(0805) vout pok load vout = 1v (ac coupled) output ripple at 20mhz bandwidth conditions vin = 12v, cin = 3x22f (1206), cout = 3x47f + 100f (1206) vout = 1.8v (ac coupled) vout = 3.3v (ac coupled) load = 0a 20mv / div vout = 1v (ac coupled) output ripple at 20mhz bandwidth conditions vin = 12v, cin = 3x22f (1206), cout = 3x47f + 100f (1206) vout = 1.8v (ac coupled) vout = 3.3v (ac coupled) load = 10a 20mv / div vout = 1v (ac coupled) output ripple at 500mhz bandwidth conditions vin = 12v, cin = 3x22f (1206), cout = 3x47f + 100f (1206) vout = 1.8v (ac coupled) vout = 3.3v (ac coupled) load = 0a 20mv / div vout = 1v (ac coupled) output ripple at 500mhz bandwidth conditions vin = 12v, cin = 3x22f (1206), cout = 3x47f + 100f (1206) vout = 1.8v (ac coupled) vout = 3.3v (ac coupled) load = 2a 20mv / div vout = 1v (ac coupled) output ripple at 500mhz bandwidth conditions vin = 12v, cin = 3x22f (1206), cout = 3x47f + 100f (1206) vout = 1.8v (ac coupled) vout = 3.3v (ac coupled) load = 6a 20mv / div
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 12 typical performance characteristics vout = 1v (ac coupled) output ripple at 500mhz bandwidth conditions vin = 12v, cin = 3x22f (1206), cout = 3x47f + 100f (1206) vout = 1.8v (ac coupled) vout = 3.3v (ac coupled) load = 10a 20mv / div vout (ac coupled) load transient from 0 to 5a (v out =1v) conditions vin = 12v, vout = 1.0v cin = 3 x 22f (1206) cout = 3 x 47f (0805) + 3 x 22f (0805) using best performance configuration load vout (ac coupled) load transient from 0 to 10a (v out =1v) conditions vin = 12v, vout = 1.0v cin = 3 x 22f (1206) cout = 3 x 47f (0805) + 3 x 22f (0805) using best performance configuration load vout (ac coupled) load transient from 0 to 15a (v out =1v) conditions vin = 12v, vout = 1.0v cin = 3 x 22f (1206) cout = 3 x 47f (0805) + 3 x 22f (0805) using best performance configuration load vout (ac coupled) load transient from 0 to 5a (v out =3.3v) conditions vin = 12v, vout = 3.3v cin = 3 x 22f (1206) cout = 3 x 47f (0805) + 3 x 22f (0805) using best performance configuration load vout (ac coupled) load transient from 0 to 10a (v out =3.3v) conditions vin = 12v, vout = 3.3v cin = 3 x 22f (1206) cout = 3 x 47f (0805) + 3 x 22f (0805) using best performance configuration load
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 13 typical performance characteristics vout (ac coupled) load transient from 0 to 15a (v out =3.3v) conditions vin = 12v, vout = 3.3v cin = 3 x 22f (1206) cout = 3 x 47f (0805) + 3 x 22f (0805) using best performance configuration load vout (ac coupled) load transient from 0 to 5a (v out =3.3v) conditions vin = 12v, vout = 3.3v cin = 3 x 22f (1206) cout = 3 x 47f (1206) + 100f (1206) using best performance configuration load vout (ac coupled) load transient from 0 to 10a (v out =3.3v) conditions vin = 12v, vout = 3.3v cin = 3 x 22f (1206) cout = 3 x 47f (1206) + 100f (1206) using best performance configuration load vout (ac coupled) load transient from 0 to 15a (v out =3.3v) conditions vin = 12v, vout = 3.3v cin = 3 x 22f (1206) cout = 3 x 47f (1206) + 100f (1206) using best performance configuration load
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 14 functional block diagram soft start power good logic band gap reference voltage reference generator compensation network thermal limit uvlo current limit gate drive pll/sawtooth generator fadj enable ss agnd pok avin vfb pgnd vout nc(sw) pvin s_in error amp pwm comp (+) (-) (-) (+) digital i/o s_out to pll linear regulator avino 300k 180k m/s compensation network eain pg btmp bgnd vddb figure 4: functional block diagram functional description synchronous buck converter the en23f0qi is a highly integrated synchronous, buck converter with integrated controller, power mosfet switches and integrated inductor. the nominal input voltage (pvin) range is 4.5v to 14v and can support up to 15a of continuous output current. the output voltage is programmed using an external resistor divider network. the control loop utilizes a type iv voltage-mode compensation network and maximizes on a low-noise pwm topology. much of the compensation circuitry is internal to the device. however, a phase lead capacitor is required along with the output voltage feedback resistor divider to complete the type iv compensation network.. the high switching frequency of the en23f0qi enables the use of small size input and output capacitors, as well as a wide loop bandwidth within a small foot print. protection features: the power supply has the following protection features: ? programmable over-current protection ? thermal shutdown with hysteresis ? under-voltage lockout protection additional features: ? switching frequency synchronization ? programmable soft-start ? power ok output monitoring power up sequence the en23f0qi is designed to be powered by either a single input supply (pvin) or two separate
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 15 supplies: one for pvin and the other for avin. single input supply application (pvin): figure 5. single supply applications circuit the en23f0qi has an internal linear regulator that converts pvin to 3.3v. the output of the linear regulator is provided on the avino pin once the device is enabled. avino should be connected to avin on the en23f0qi. in this application, the following external components are required: place a 1f, x5r/x7r, capacitor between avino and agnd as close as possible to avino. place a 0.1f, x5r/x7r, capacitor between avin and agnd as close as possible to avin. in addition, place a resistor (r vb ) between vddb and avin, as shown in figure 5. enpirion recommends r vb =4.75k ? . in this application, enable cannot be asserted before pvin. if no external enable signal is used, tying enable to avin meets this requirement. dual input supply application (pvin and avin): figure 6: dual input supply application circuit in this application, place a 0.1f, x7r, capacitor between avin and agnd as close as possible to avin. refer to figure 6 for a recommended schematic for a dual input supply application. for dual input supply applications, the sequencing of the two input supplies, pvin and avin, is very important. during power up, neither enable nor pvin should be asserted before avin. there are two common acceptable turn-on/off sequences for the device. enable can be tied to avin and come up with it, and pvin can be ramped up and down as needed. alternatively, pvin can be brought high after avin is asserted, and the device can be turned on and off by toggling the enable pin. pvin may be applied before avin if enable is toggled after both pvin and avin is applied. enable operation the enable pin provides a means to enable normal operation or to shut down the device. a logic high will enable the converter into normal operation. when the enable pin is asserted (high) the device will undergo a normal soft-start, allowing the output voltage to rise monotonically into regulation. a logic low will disable the converter and the device will power down in a controlled manner. the enable signal has to be low for at least the enable lockout time (8ms) in order for the device to be re-enabled. pre-bias precaution the en23f0qi is not designed to be turned on into a pre-biased output voltage. be sure the output capacitors are not charged or the output of the en23f0qi is not pre-biased when the en23f0qi is first enabled. frequency synchronization the switching frequency of the en23f0qi can be phase-locked to an external clock source to move unwanted beat frequencies out of band. the internal switching clock of the en23f0qi can be phase locked to a clock signal applied to the s_in pin. an activity detector recognizes the presence of an external clock signal and automatically phase- locks the internal oscillator to this external clock. phase-lock will occur as long as the input clock frequency is in the range of 0.8mhz to 1.6mhz. when no clock is present, the device reverts to the free running frequency of the internal oscillator. adding a resistor (r fs ) to the fadj pin will adjust the switching frequency. if a 3k ? resistor is placed on fadj the nominal switching frequency of the en23f0qi is 1mhz. figure 7 shows the typical r fs resistor value versus switching frequency.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 16 figure 7 . r fs versus switching frequency the efficiency performance of the en23f0qi for various vouts can be optimized by adjusting the switching frequency. table 1 shows recommended r fs values for various vouts in order to optimize performance of the en23f0qi. pvin vout r fs 12v 1.0v 3k 1.2v 3.3k 1.8v 4.87k 2.5v 10k 3.3v 15k table 1: recommended r fs values spread spectrum mode the external clock frequency may be swept between 0.8mhz and 1. 6mhz at repetition rates of up to 10 khz in order to reduce emi frequency components. soft-start operation soft start is a means to ramp the output voltage gradually upon start-up. the output voltage rise time is controlled by the choice of soft-start capacitor, which is placed between the ss pin (pin 78) and the agnd pin (pin 74). rise time (ms): t r c ss [nf] x 0.06 during start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10a. typical soft-start rise time is ~2.8ms with ss capacitor value of 47nf. the rise time is measured from when v in > v uvlor and enable pin voltage crosses its logic high threshold to when v out reaches its programmed value. pok operation the pok signal is an open drain signal (requires a pull up resistor to avin or similar voltage) from the converter indicating the output voltage is within the specified range. typically, a 100k ? or lower resistance is used as the pull-up resistor. the pok signal will be logic high (avin) when the output voltage is above 90% of the programmed voltage level. if the output voltage is below this point, the pok signal will be a logic low. the pok signal can be used to sequence down-stream converters by tying to their enable pins. over-current protection (ocp) the current limit function is achieved by sensing the current flowing through a sense pfet. when the sensed current exceeds the current limit, both power fets are turned off for the rest of the switching cycle. if the over-current condition is removed, the over-current protection circuit will re- enable pwm operation. if the over-current condition persists, the circuit will continue to protect the load. the ocp trip point is nominally set as specified in the electrical characteristics table. in the event the ocp circuit trips consistently in normal operation, the device enters a hiccup mode. while in hiccup mode, the device is disabled for a short while and restarted with a normal soft-start. the hiccup time is approximately 32ms. this cycle can continue indefinitely as long as the over current condition persists. the ocp trip point can be programmed to trip at a lower level via the rclx pin. the value of the resistor connected between rclx and ground will determine the ocp trip point. generally, the higher the rclx value, the higher the current limit threshold. note that if rclx pin is left open the output current will be unlimited and the device will not have current limit protection. reference table 2 for a list of recommended resistor values on rclx that will set the ocp trip point at the typical value of 22.5a, also specified in the electrical characteristics table. v out range r clx value 0.6v < v out 0.9v 36.5k 0.9v < v out 1.2v 38.4k 1.2v < v out 2.0v 40.2k 2.0v < v out 5.0v 45.3k table 2: recommended r clx values vs. v out 0.600 0.800 1.000 1.200 1.400 1.600 1.800 0 2 4 6 8 10121416182022 switching frequency (mhz) r fs resistor value (k ? ) rfs vs. sw frequency conditions v in = 6v to 12v v out = 0.8v to 3.3v
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 17 thermal overload protection thermal shutdown circuit will disable device operation when the junction temperature exceeds approximately 150oc. after a thermal shutdown event, when the junction temperature drops by approx 20oc, the converter will re-start with a normal soft-start. input under-voltage lock-out (uvlo) internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage. hysteresis, input de- glitch and output leading edge blanking ensures high noise immunity and prevents false uvlo triggers. master / slave (parallel) operation: up to four en23f0qi devices may be connected in a master/slave configuration to handle larger load currents. the maximum output current for each parallel device will need to be de-rated by 20 percent so that no devices will over current due to current mis-match. the master device?s switching clock may be phase-locked to an external clock source via the s_in pin or left open and use its default switching frequency. the device is placed in master mode by pulling the m/s pin low or in slave mode by pulling m/s pin high. note that the m/s pin is also pulled low for standalone mode. in master mode, the internal pwm signal is output on the s_out pin. this pwm signal from the master is fed to the slave device at its s_in input. the slave device acts like an extension of the power fets in the master. the inductor in the slave prevents crow-bar currents from master to slave due to timing delays. parallel operation in dual supply mode is shown in figure 9. single supply mode operation may also be implemented similarly. note that only critical components are shown. the red text and red lines indicate the important parallel operation connections and care should be taken in layout to ensure low impedance between those paths. the parallel current matching is illustrated in figure 8. figure 8 . parallel current matching 0 2.5 5 7.5 10 12.5 15 17.5 20 0 5 10 15 20 25 30 individual output current (a) total output current (a) parallel current share breakdown master slave ideal conditions en23f0qi v in = 12v v out = 1.2v
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 18 figure 9. parallel operation illustration
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 19 application information output voltage programming and loop compensation the en23f0qi uses a type iv voltage mode compensation network. type iv voltage mode control is a proprietary enpirion control scheme that maximizes control loop bandwidth to deliver excellent load transient responses and maintain output regulation with pin point accuracy. for ease of use, most of this network has been customized and is integrated within the device package. the en23f0qi output voltage is programmed using a simple resistor divider network (r a and r b ). the feedback voltage at vfb is nominally 0.6v. r a is predetermined based on table 5 and r b can be calculated based on figure 10. the values recommended for c out , c a , r ca and r ea make up the external compensation of the en23f0qi. it will vary with each pvin and vout combination to optimize on performance. the en23f0qi solution can be optimized for either smallest size or highest performance. please see table 5 for a list of recommended r a , c a , r ca , r ea and c out values for each solution. figure 10: v out resistor divider & compensation components. see table 5 for details. input capacitor selection the en23f0qi requires three 22f/1206 input capacitor. low-cost, low-esr ceramic capacitors should be used as input capacitors for this converter. the dielectric must be x5r or x7r rated. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. in some applications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. table 3 contains a list of recommended input capacitors. recommended input capacitors description mfg p/n 22f, 16v, x5r, 10%, 1206 murata grm31cr61c226me15 22f, 16v, x5r, 20%, 1206 taiyo yuden emk316abj226ml-t 22f, 25v, x5r, 10%, 1210 murata grm32er61e226ke15l 22f, 25v, x5r, 20%, 1210 taiyo yuden tmk325bj226mm-t table 3: recommended input capacitors output capacitor selection as seen from table 5, the en23f0qi has been optimized for use with three 47f/1206 plus one 100f/1206 for best performance. for smallest solution size, various combinations of output capacitance may be used. see table 5 for details. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and bias voltage. table 4 contains a list of recommended output capacitors. output ripple voltage is determined by the aggregate output capacitor impedance. capacitor impedance, denoted as z, is comprised of capacitive reactance, effective series resistance, esr, and effective series inductance, esl reactance. placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. n total z z z z 1 ... 1 1 1 2 1 + + + = recommended output capacitors description mfg p/n 47f, 6.3v, x5r, 20%, 1206 murata GRM31CR60J476ME19L 47f, 10v, x5r, 20%, 1206 taiyo yuden lmk316bj476ml-t 22f, 10v, x5r, 20%, 0805 panasonic ecj-2fb1a226m 22f, 10v, x5r, 20%, 0805 taiyo yuden lmk212bj226mg-t 100f, 6.3v, x5r, 20%, 1206 murata grm31cr60j107me39l taiyo yuden jmk316bj107ml-t table 4: recommended output capacitors
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 20 best performance smallest solution size c in = 3 x 22f/1206 c in = 3 x 22f/1206 c out = 3x47f (1206) + 100f(1206) ? v out 1.8v, c out = 22f/0805 + 2x47f/0805 3.3v > v out > 1.8v, c out = 3x47f/1206 r a = 200 k ? r a = 100 k ? pvin (v) vout (v) c a (pf) r ca (k ? ) r ea (k ? ) ripple (mv) deviation (mv) pvin (v) vout (v) c a (pf) r ca (k ? ) r ea (k ? ) ripple (mv) deviation (mv) 14v 1.0v 15 19 0 25.6 23 14v 1.0v 12 36 open 15 78 1.2v 12 22 0 24 35 1.2v 12 36 open 18 93 1.5v 12 22 0 26.4 42 1.5v 12 36 open 22 104 1.8v 10 24 0 28.4 45 1.8v 12 36 open 25 130 2.5v 18 14 56 31.6 78 2.5v 15 27 open 32 162 3.3v 12 14 56 37.3 114 3.3v 10 27 open 46 200 12v 1.0v 18 16 0 21.6 31 12v 1.0v 22 27 open 15 84 1.2v 15 19 0 22.7 38 1.2v 22 27 open 18 97 1.5v 15 19 0 25.2 39 1.5v 18 27 open 21 118 1.8v 12 22 0 25.8 41 1.8v 18 27 open 24 130 2.5v 22 12 56 30 84 2.5v 22 27 open 30 172 3.3v 15 12 56 30.8 116 3.3v 15 27 open 43 213 10v 1.0v 18 14 0 18.8 37 10v 1.0v 56 20 open 15 85 1.2v 18 14 0 20.4 41 1.2v 47 20 open 17 100 1.5v 18 16 0 22 42 1.5v 39 20 open 20 120 1.8v 15 19 0 23.6 46 1.8v 33 20 open 22 140 2.5v 27 10 56 26.5 90 2.5v 33 20 open 29 177 3.3v 22 10 56 28.9 122 3.3v 22 20 open 41 230 8v 1.0v 22 10 0 17.2 17.2 8v 1.0v 200 10 open 14 83 1.2v 22 13 0 18.7 18.7 1.2v 200 10 open 16 90 1.5v 18 15 0 20.1 20.1 1.5v 150 10 open 19 107 1.8v 18 15 0 20.9 20.9 1.8v 82 10 open 20 138 2.5v 39 6 56 23.6 23.6 2.5v 68 10 open 27 178 3.3v 27 6 56 22.8 22.8 3.3v 39 10 open 36 239 6.6v 1.0v 27 10 0 13.8 13.8 6.6v 1.0v 200 10 open 13 99 1.2v 27 10 0 15.2 15.2 1.2v 200 10 open 15 105 1.5v 22 13 0 16.4 16.4 1.5v 200 10 open 17 118 1.8v 22 13 0 19.6 19.6 1.8v 150 10 open 19 138 2.5v 47 4 56 20.4 20.4 2.5v 100 10 open 24 183 3.3v 39 4 56 21.1 21.1 3.3v 56 10 open 32 250 5v 1.0v 33 10 0 12.4 12.4 5v 1.0v 200 10 open 12 123 1.2v 33 10 0 13.4 13.4 1.2v 200 10 open 13 132 1.5v 27 13 0 14.3 14.3 1.5v 200 10 open 16 145 1.8v 27 13 0 15.4 15.4 1.8v 200 10 open 17 156 2.5v 68 1 56 15.5 15.5 2.5v 100 10 open 20 216 3.3v 47 1 56 12.9 12.9 3.3v 100 10 open 21 253 table 5: r a , c a , r ca and r ea values for various pvin/vout combinations : best performance vs. smallest solution size. use the equations in figure 10 to calculate r b . note 6 : output ripple is measured at no load and nominal deviation is for a 15a load transient step. note 7 : for compensation values of output voltage in between the specified output voltages, choose compensation values of the lower output voltage setting.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 21 thermal considerations thermal considerations are important power supply design facts that cannot be avoided in the real world. whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be accounted for. the enpirion powersoc helps alleviate some of those concerns. the enpirion en23f0qi dc-dc converter is packaged in an 8x11x3mm 68-pin qfn package. the qfn package is constructed with copper lead frames that have exposed thermal pads. the exposed thermal pad on the package should be soldered directly on to a copper ground pad on the printed circuit board (pcb) to act as a heat sink. the recommended maximum junction temperature for continuous operation is 125c. continuous operation above 125c may reduce long-term reliability. the device has a thermal overload protection circuit designed to turn off the device at an approximate junction temperature value of 150c. the en23f0qi is guaranteed to support the full 4a output current up to 85c ambient temperature. the following example and calculations illustrate the thermal performance of the en23f0qi. example: v in = 12v v out = 1.2v i out = 15a first calculate the output power. p out = 1.2v x 15a = 18w next, determine the input power based on the efficiency ( ) shown in figure 11. figure 11: efficiency vs. output current for v in = 12v, v out = 1.2v at 15a, 80% = p out / p in = 80% = 0.8 p in = p out / p in 18w / 0.8 22.5w the power dissipation (p d ) is the power loss in the system and can be calculated by subtracting the output power from the input power. p d = p in ? p out 22.5w ? 18w 4.5w with the power dissipation known, the temperature rise in the device may be estimated based on the theta ja value ( ja ). the ja parameter estimates how much the temperature will rise in the device for every watt of power dissipation. the en23f0qi has a ja value of 13 oc/w without airflow. determine the change in temperature ( t) based on p d and ja . t = p d x ja t 4.5w x 13c/w = 58.5c 59c the junction temperature (t j ) of the device is approximately the ambient temperature (t a ) plus the change in temperature. we assume the initial ambient temperature to be 25c. t j = t a + t t j 25c + 59c 84c the maximum operating junction temperature (t jmax ) of the device is 125c, so the device can operate at a higher ambient temperature. the maximum ambient temperature (t amax ) allowed can be calculated. t amax = t jmax ? p d x ja 125c ? 59c 66c the maximum ambient temperature the device can reach is 66c given the input and output conditions. note that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate. 0 10 20 30 40 50 60 70 80 90 100 0123456789101112131415 efficiency (%) output current (a) efficiency vs. output current vout = 3.3v vout = 1.8v vout = 1.2v conditions v in = 12.0v avin = 3.3v dual supply
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 22 engineering schematic figure 12: critical components engineering schematic
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 23 layout recommendation figure 13: top layer of engineering board (top view). recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en23f0qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en23f0qi should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: the pgnd connections for the input and output capacitors on layer 1 need to have a slit between them in order to provide some separation between input and output current loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. recommendation 4 : the thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. the drill diameter of the vias should be 0.33mm, and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. recommendation 5 : multiple small vias (the same size as the thermal vias discussed in recommendation 4) should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias along the edge of the gnd copper closest to the +v copper. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. if vias cannot be placed under the capacitors, then place them on both sides of the slit in the top layer pgnd copper. recommendation 6 : avin is the power supply for the small-signal control circuits. it should be connected to the input voltage at a quiet point. in figure 13 this connection is made at the input capacitor. recommendation 7 : the layer 1 metal under the device must not be more than shown in figure 13. refer to the section regarding exposed metal on bottom of package. as with any switch-mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 8: the v out sense point should be just after the last output filter capacitor. keep the sense trace short in order to avoid noise coupling into the node. contact enpirion technical support for any remote sensing applications. recommendation 9 : keep r a , c a , r b , and r ca close to the vfb pin (refer to figure 13). the vfb pin is a high-impedance, sensitive node. keep the trace to this pin as short as possible. whenever possible, connect r b directly to the agnd pins 52 and 53 instead of going through the gnd plane. recommendation 10 : follow all the layout recommendations as close as possible to optimize performance. enpirion provides schematic and layout reviews for all customer designs. contact enpirion applications engineering for detailed support (techsupport@enpirion.com).
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 24 design considerations for lead-frame based modules exposed metal on bottom of package lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package, as shown in figure 14. only the thermal pad and the perimeter pads are to be mec hanically or electrically connected to the pc board. the pcb top layer under the en23f0qi should be clear of any metal (copper pours, traces, or vias) except for the thermal pad. the ?shaded-out? area in figure 14 represents the area that should be clear of any metal on the top layer of the pcb. any layer 1 metal under the shaded-out area runs the risk of undesirable shorted connections even if it is covered by soldermask. the solder stencil aperture should be smaller than the pc b ground pad. this will prevent excess solder from causing bridging between adjacent pins or other exposed metal under the package. please consult the enpirion manufacturing application note for more details and recommendations. figure 14: lead-frame exposed metal (bottom view) shaded area highlights exposed metal that is not to be me chanically or electrically connected to the pcb.
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 25 recommended pcb footprint figure 15: en23f0qi pcb footprint (top view) ?
en23f0qi ? enpirion 2012 all rights reserved, e&oe enpirion confidential www.enpirion.com , page 26 package and mechanical figure 16: en23f0qi package dimensions (bottom view) packing and marking information : http://www.enpirion.com/resource-center-packing-and-marking-information.htm contact information enpirion, inc. perryville iii corporate park 53 frontage road - suite 210 hampton, nj 08827 usa phone: 1.908.894.6000 fax: 1.908.894.6090 enpirion reserves the right to make changes in circuit design and/or specif ications at any time without notice. information fur nished by enpirion is believed to be accurate and reliable. enpirion assumes no respons ibility for its use or for infringement of patents or other th ird party rights, which may result from its use. enpirion products are not authorized for us e in nuclear control systems, as critical components in life su pport systems or equipment used in hazardous environment without the ex press written authority from enpirion ?

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